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  #1  
Old 01-28-2008, 07:35 PM
Grant Stockly Grant Stockly is offline
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Default Mini680 Altair 680 Memory Expansion Board

As a "promotion" to the Altair 680 buyers I promised a 32k RAM upgrade. Due to the wait they have had to endure, I've decided to add 512k of Flash memory.
  • The memory is available from 0x0000 to 0x7FFF.
  • There is a 2k gap from 0x8000 to 0x87FF to allow for the onboard 1k of memory AND the optional vintage 2k RAM upgrade.
  • The flash memory is available from 0x8800 to 0xC7FF. This is a 16k window.
  • There is a page register (IC U6) at 0xC8FF to select which of the 32 16k pages you want to access.
What does this mean to non-programmers? It means a bone stock Altair with the upgrade will have 33,792 bytes of RAM instead the stock 1024 bytes.

It also means you will be able to boot Basic and the Assembler/Editor without loading a paper tape image. There is also MORE than enough space in 512k for any other data.

So far the only software I have is the Assembler/Editor and two versions of Basic. These won't even use up the first 16k of Flash.

When I tried to assemble these boards, I noticed DigiKey sent me 25 $5 ADC chips instead of 25 $.60 74ALS574s. I am ordering 25 of the correct chip to be shipped FedEx overnight so that I can move forward with getting your kits out the door!

The PCB design, PLD logic code, schematics, etc will all be available for anyone to modify. The PLD is socketed for easy reprogramming.

Here are some pictures, sorry...I don't have one with it installed...

The configuration below shows the required parts for only the 32k memory expansio. The only parts required for flash is the flash itself and the page register.


The upgrade card plugs into the processor socket on the PCB, and the processor plugs into the PCB.


This is what I had to do to make sure the PCB design worked!
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  #2  
Old 01-28-2008, 07:40 PM
Grant Stockly Grant Stockly is offline
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Code:
Name     Mini680 ;
PartNo   00 ;
Date     1/26/2008 ;
Revision 01 ;
Designer Grant Stockly ;
Company  Stockly Electronics ;
Assembly None ;
Location None ;
Device   G22V10 ;

/**** INPUT PINS ********************* DESCRIPTION *************************/
PIN   1 = CLK1                    ; /* Clock Phase 1                       */
PIN   2 = RWi                     ; /* R/W from Processor                  */
PIN   3 = VMA                     ; /* Valid Memory Address                */
PIN   4 = ADDRAND                 ; /* Output of BA0...7 NAND Gate         */
PIN   5 = HALT                    ; /* 1k memory low jumper (not used)     */
PIN   6 = CLK2                    ; /* Clock Phase 2                       */
PIN   7 = A10                     ; /* Buffered Address bit 10             */
PIN   8 = A11                     ; /* Buffered Address bit 11             */
PIN   9 = A12                     ; /* Buffered Address bit 12             */
PIN  10 = A13                     ; /* Buffered Address bit 13             */
PIN  11 = A14                     ; /* Buffered Address bit 14             */
PIN  13 = A15                     ; /* Buffered Address bit 15             */
/*** OUTPUT/INPUT PINS *************** DESCRIPTION *************************/
PIN  23 = BE                      ; /* Mini680 Data Buffer Enable          */
PIN  22 = RD                      ; /* Read Strobe for Flash and RAM       */
PIN  21 = WR                      ; /* Write Strobe for Flash and RAM      */
PIN  20 = FLASH_CS                ; /* Flash Memory Chip Select            */
PIN  19 = RAM_CS                  ; /* RAM Chip Select                     */
PIN  18 = PAGE                    ; /* Write Strobe to Page Register       */
PIN  17 = RWo                     ; /* R/W to Motherboard                  */
PIN  16 = NC                      ; /* No Connect (free output/input)      */
PIN  15 = A8                      ; /* Buffered Address bit 8              */
PIN  14 = A9                      ; /* Buffered Address bit 9              */
/***************************************************************************/

Field Address = [A15..8];

/***********************************************/
/***** Handle Front Panel Operation of RAM *****/
/***********************************************/
/*****************************************************************/
/* When HALT is low, RWo needs to be an input for writing to RAM */
/*****************************************************************/
RWo.OE = HALT;

/*************************************************************/
/***** Generate Read and Write Strobes for Flash and RAM *****/
/*************************************************************/
/******************************************************************/
/* RWi - R/W input from processor - HIGH=READ, LOW=WRITE          */
/* CLK2 is the synchronous bus clock and is active HIGH           */
/*      CLK2 must be high for a memory operation                  */
/* VMA indicates a stable and valid memory address is on the bus, */
/*      flash may require this                                    */
/* VMA is required for Flash and Page writes only                 */
/******************************************************************/
!RD = ((RWi & HALT) & CLK2)         /* Normal Operation RD Control */
    # (RWo & CLK2 & !HALT);         /* Front Panel RD Control */
                              /* Normal Operation WR Control */
!WR = ((!RWi & HALT) & CLK2 & ((VMA & !FLASH_CS) # !RAM_CS # !PAGE))
                              /* Front Panel WR Control */
    # (!RWo & CLK2 & ((VMA & !FLASH_CS) # !RAM_CS # !PAGE) & !HALT);

/*********************************************************/
/***** Generate Write Strobe for Flash Page Register *****/
/*********************************************************/
/*********************************************************************************/
/* Input ADDRAND is an 8 input NAND gate with A7-0 as inputs                     */
/* When [Address=C8xx] and [Address=xxFF] and [write] and [valid memory address] */
/*********************************************************************************/
!PAGE = Address:[C800] & !ADDRAND & !RWi & CLK2 & VMA;

/***************************************************/
/***** Generate Chip Selects for Flash and RAM *****/
/***************************************************/
/*****************************************************************/
/* RAM is from Address 0x0000 to 0x7FFF                          */
/* Space for optional internal RAM from Address 0x8000 to 0x87FF */
/* Flash is from Address 0x8800 to 0xC7FF                        */
/*****************************************************************/
!RAM_CS = !A15 ;

/* Flash is from Address 0x8800 to 0xC7FF */
!FLASH_CS = Address:[8800..C700];

/**********************************************/
/***** Generate R/W output to Motherboard *****/
/**********************************************/
/***************************************************************************/
/* When [RAM_CS] or [FLASH_CS] or [PAGE] (are addressed), make WRo low     */
/*      This is required to keep the motherboard data buffers in the WRITE */
/*      direction                                                          */
/* RWo needs to be LOW when accessing external memory                      */
/***************************************************************************/
RWo = (RAM_CS & FLASH_CS & PAGE) & RWi;

/***************************************************************/
/***** Generate direction output for Flash/RAM data buffer *****/
/***************************************************************/
/**************************************************************************/
/* BE MUST be high unless the 6800 is addressing and reading Flash or RAM */
/* When BE is high, the buffer is going from the 6800 to the memory chips */
/* BE needs to be HIGH when accessing external memory                     */
/**************************************************************************/
!BE = !(RAM_CS & FLASH_CS & PAGE) & !RD;

Last edited by Grant Stockly; 01-28-2008 at 07:42 PM.
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  #3  
Old 02-06-2008, 02:20 PM
bugman bugman is offline
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Default Basic

I probably should wait to ask questions until I recieve (and build) my kit because I bet the answers will be obvious, but I can't help myself.

I understand how assembled machine code will be able to be stored on the flash. I guess that it would stand to reason that a basic program, or vtl-2 program could be stored as well if you know the memory locations that they initially reside in?

-Brian
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  #4  
Old 02-06-2008, 06:09 PM
Grant Stockly Grant Stockly is offline
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Quote:
Originally Posted by bugman View Post
I probably should wait to ask questions until I recieve (and build) my kit because I bet the answers will be obvious, but I can't help myself.

I understand how assembled machine code will be able to be stored on the flash. I guess that it would stand to reason that a basic program, or vtl-2 program could be stored as well if you know the memory locations that they initially reside in?
Currently VTL and basic will not store programs to the flash.

The flash can easily be reprogrammed by anyone, so an upgrade in the future would be easy. VTL would be hard to patch, but basic might be possible. What I would imagine is taking the KCACR basic (Kansas City cassette tape standard) and modifying the save/load routines to go to flash instead of the tape. I'm not sure how hard this would be. Once the first kits are built by I'm sure the builders will do some programming. Is that something you would be interested in doing? We'd probably have to run basic in an emulator and trace the routines when issuing the commands, and then substitute our own code.

Along with save/load, it would be nice to have a "directory" type function...
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  #5  
Old 02-06-2008, 07:37 PM
bugman bugman is offline
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I think this would be a valuable effort. When I asked the question, I guess I was thinking about the challenge on a simpler level. Just identifying what block of RAM gets updated when you type in a basic or VTL program. Then transfering that block to the flash to be re-deposited later. But, I am accustomed to working with slightly more advanced systems which have some form of DOS, or a monitor system that includes built in instructions for relocating blocks of memory. Probably not that simple, though. Either way, I would like to look into this once I get a kit up and running and gain some experience with how things work.
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  #6  
Old 02-10-2008, 05:21 PM
bugman bugman is offline
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Can anyone comment on their experience and preference with 6800 emulators? I think I have found the majority of the ones available on the net. So far, its looks like the one called "hippy" would be best since you can define any devices you want via c++ (rom, ram, acia, etc). Should be able to set up a system almost identical to Grant's configuration. Does anyone have experience with this emulator, and maybe even have some devices created for terminal output that I could use as examples?
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  #7  
Old 05-31-2008, 03:36 PM
bugman bugman is offline
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Hey Grant,

Received my kit today, thanks. Just wondering if you could post that memory information. When I get my kit built, I'd like to start working on the memory upgrade (unless you plan on having those in the near future). I found some plans for a simple 32k expansion for the 680 swtpc. But I'm not sure if it is 100% compatable with the altair, or how I would interface it. It uses an expansion slot, where as you use the clever IC replacement method.

Any help or direction would be appreciated.

Thanks,
Brian
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  #8  
Old 05-31-2008, 11:32 PM
Grant Stockly Grant Stockly is offline
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No problem. I was going to include assembler listings in the manual but it would have been a lot of pages for only a few people.

I have written the monitor, boot loader, flash read/write routines, and page code in modules and I have batch files that assemble the batch files into one big file for a chip burner.

I DO have a small program which writes one 8k block at a time for people wanting to add their own programs to the 680.

Look in the manual at the end of my color guide for a quick intro to the special functions in my modified monitor. Its possible to boot basic with only a few key strokes and 5 seconds.

Booting basic the vintage way involved 13 minutes with a tape cassette player OR 30+ minutes with a paper tape reader. (and you weren't guaranteed that it would work the first time!)
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  #9  
Old 01-03-2009, 10:44 PM
Grant Stockly Grant Stockly is offline
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I've been intending to get this information to you guys for a while. I wanted to wait until I could clean up the information and make it more presentable, but if I did that then it wouldn't be out for another 6 months!

So, here is a zip file with all of the data that I used to make the memory device. There are assembly files, batch files, hex code files, binary files, etc. I'll try to describe how it works. I never made it a clean process, just "got it done" for the memory card and moved on.
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  #10  
Old 01-04-2009, 08:31 PM
Grant Stockly Grant Stockly is offline
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Here are the files. I will try to make sense of them and describe what I did in a little bit. : )

The assembler code for writing to a page is in flash_burner.asm, look at the file for start/end offsets. The KNOCK macro disables write protection for a single page write.

flash_mon.asm is the stock Altair 680 ROM monitor modified for use with the flash memory.

flash_boot.asm copies the ROM monitor out of flash and into memory for execution.

page_set.asm is located on every single flash page except 0. If the computer boots up with the page register in something other than 0, this code will cause it to go to page 0 and execute the monitor.

I will describe everything required to assemble a new rom set or patch the flash with a new memory image later...
Attached Files
File Type: zip Mini680 Release Data.zip (284.1 KB, 275 views)
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