Museum restoration of 8800

[marty]

Hi Phil;
I would NOT recemend the 4K Dynamic Memory Boards, Maybe by Rev. 2 , they fixed the Problems, I would use Static memory boards, I had a 16K Dynamic Memory Board, when I had my 8800b, and it never worked, right or well. It would pass Altair memory tests, but it would not hold any thing for very long.... This was back when I bought it new in 1977, I don't have it any more... nor the Altair 8800b, I have one of Grants kits with Static memory, they work much better. Thank You Marty

[philrrtx]

Originally Posted by marty

Hi Phil;
I would NOT recemend the 4K Dynamic Memory Boards

Actually, I misspoke when I said they were the 4K dynamic boards. They are actually 4K synchronous boards, which I believe use static RAM chips. In any event, I finally figured out how the address switches work and it appears that all four are functional.

I have a front panel LED that is dead, but with the CPU and memory boards working, I'm hoping to be able to wrap this project up without too much difficulty.

[philrrtx]

I reached the point where I wanted to run a memory test program and discovered two very annoying deficiencies (IMHO) with the 8080 instruction set.

The first annoyance is that the DCX (double register decrement) instruction doesn't set the condition flags based on the outcome of the subtract operation. That makes it less than convenient for use as a 16-bit loop counter. You have to explicitly check to see if both bytes are zero to find out whether you've reached the end of the loop. If the DCX automatically set the condition flags, you could just follow it with a JZ or JNZ to continue or exit the loop. Likewise the INX doesn't set condition flags, but the single register versions (INR/DCR) do. The 8080/8085 programming manual mentioned this as being a feature, but it's hard for me to figure out why they made it that way.

The other annoying thing I found was the behavior of the HLT instruction. I was basically transcoding a memory test I wrote for the PDP-8, where errors lead to halts, and a complete successful pass likewise leads to a halt. The idea is that when the program stops you can see what address it halted at to determine whether it detected an error or was successful. Unfortunately, when the 8080 enters a HLT on the Altair, the address bus gets tri-stated and you can't read the memory address you stopped at. You also can't restart the program without executing a Reset, because Intel made the HLT essentially a "wait for interrupt" instruction. The solution that I resorted to was to replace the HLTs with JMP $. When the program hangs in a tight (very tight) loop, you can at least press Stop and read what address it is looping on to see if you got an error or not.

In any event, my four 4KB synchronous memory cards all pass the test successfully, so it's on to trying to get the Processor Technology 3P+S I/O card working.

Has anyone heard from Grant lately? I sent him e-mail to the address on the web site before I joined the forums, then sent him a PM here, but haven't had a response to either. I'd like to find out what the prospects are of the museum buying a case and dress front panel from him for our box.

[philrrtx]

After a few bumps and stops, I have the Processor Technology 3P+S I/O card working via an RS232 interface with an LSI ADM-3A CRT (a nice terminal contemporary to the Altair). Whoever had this card previously apparently didn't understand just how it worked, because s/he had installed a 7404 inverter chip in an (thoughtfully provided by PT) empty IC slot and had run the TBE (Transmit Buffer Empty) and RDA (Receive Data Available) signals from the UART through it before putting them on the data bus. This made them much more difficult to detect at the CPU (they show up as 0s instead of 1s).

I removed the inverters, after which the PT serial test code almost worked. It was supposed to output lines of characters from 30H to 55H, with or without a delay as determined by a sense switch. You could then set a different sense switch and it would jump to the input test, where it received characters and echoed them back to the interface. Yet a different switch indicated the test was over, resulting in a jump to a HLT. Mine would output one character, input one character, then halt. This was tracked to a failing read of the sense switches. They were all coming in as ONEs, no matter how they were set. When I replaced the sense switch reads with NOPs, the test code worked perfectly, and I could send and receive characters with the terminal.

Some scope probing today reveals that a 7404 inverter chip on the front panel control board appears to be bad; it isn't passing the SNSW read enable signal. I'll need to replace the chip to proceed any further.

BTW, I notice that the front panel control board relies on behavior that I couldn't find described anywhere in the 8080 documentation, and that is that the device address (the argument to an IN or OUT statement) gets sent out on both the high and low bytes of the address bus. The 3P+S I/O card, for example, looks for its address on A0-A7, but the logic for the sense switch read looks for 0FFH on A8-A15. Nothing I found in either the Altair or 8080 documentation states that this is the chip's normal behavior on I/O statements.

[philrrtx]

I finally got the sense switch read problem sorted out. It turned out to be the 74L30 chip that detected all ONEs on A15-A8 (the I/O device address). I didn't have a 74L30 ready at hand, so currently have a 7430 in the socket. The only disadvantage of that I can think of is it presents a higher loading on the address bus. I'll replace it with the low-power chip as soon as we acquire one.

So, everything seemed to be working correctly. I was able to poke in the test routines for the 3P+S I/O card and the program was responding to the sense switches properly. I put the front panel back on and everything went to hell in a handbasket. The 4K memory card at 0000 disappeared, and one started showing up at 16K, which should have been impossible. It seemed almost like the address bus was screwed up, but there have been no changes to any of that wiring, and the LEDs are giving the correct indications.

After some experimenting, I managed to get three of the 4K memory boards working in the 0–12K range, but the fourth card would not come up at 12K. From what I have read in a number of forum postings (other forums, not here), these 88-S4K cards had a lot of problems, and were sensitive to timing problems, so that may be what's causing the behavior I see. Puzzling, however, is that the whole set of four 4K cards used to work and even passed an intensive memory test. I reached my frustration threshold today, and put the mess aside to work on another project for a while. Grrrrrr...!

[marty]

Hi PHIL:
Could you please post the programs you are using here for the rest of us ????
Also, I have not had any problems with any of my 4k memory cards...
have you tried each card at all the addresses that you intend to use,,, maybe one or more is mapping to more than one address... THANK YOU Marty

[philrrtx]

Originally Posted by marty

Hi PHIL:
Could you please post the programs you are using here for the rest of us ????
Also, I have not had any problems with any of my 4k memory cards...
have you tried each card at all the addresses that you intend to use,,, maybe one or more is mapping to more than one address... THANK YOU Marty

The failing card is correctly detecting its starting address, which can be viewed with a scope at the test point just left of the address switches. I also can see the bus driver disable signal being negated, so it should be putting data on the bus, yet it looks like the bus is floating. We have decided not to worry about fixing it at this point. The 12K we have working is sufficient for our purposes.

The test programs for the 3P+S I/O board I have been using are in the documentation I found for it on Dave Dunfield's site. See http://www.classiccmp.org/dunfield/s100c/ptco/3pps.pdf

Here's the memory test program I wrote:

                     INSTRUCTION
LABEL	ADR	OCTAL		MNEMONIC	DESCRIPTION
	000	052 051 000	LHLD COUNT	Get number of locations to write
	003	353		XCHG		Move to DE registers
	004	052 053 000	LHLD START	Get starting address
LOOP	007	072 047 000	LDA BYTE1	Get first byte to write
	012	167		MOV M, A	Write in memory address
	013	226		SUB M		Read memory and subtract
	014	312 022 000	JZ CONT1	OK if zero
ERR1	017	303 017 000	JMP ERR1	Error if loops here
CONT1	022	072 050 000	LDA BYTE2	Get second byte to write
	025	167		MOV M, A	Write in memory address
	026	226		SUB M		Read memory and subtract
	027	312 035 000	JZ CONT2	OK if zero
ERR2	032	303 032 000	JMP ERR2	Error if loops here
CONT2	035	043		INX  H		Increment write address
	036	033		DCX D		Decrement count
	037	172		MOV A, D	Check if DE=0
	040	263		ORA E		       by ORing D with E
	041	302 007 000	JNZ LOOP	Go around again
GOOD	044	303 044 000	JMP GOOD	Good if loops here
BYTE1	047	252				First byte to write = 10 101 010
BYTE2	050	125				Second byte to write = 01 010 101
COUNT	051	323 037				Count = 16339
START	053	055 000				Start address

START must contain the first location past the program. COUNT must contain the total memory you have available minus the length of the program (remember, least significant byte first). The test is good if it loops at GOOD. An error has been detected if it loops at either ERR1 or ERR2.