Test Board

[Reactive]

Glenn: I do have ISE and ispLever. I found ISE totally confusing. ispLever was a little better, but I still found it and Quartus a bit confusing. Probably due to the fact that I haven't really used anything close to them before. Grant found some videos that I've watched that helped a bit. Think they are still on my Site too if you'd like to see them.

After reading a few reviews and talking a few different people who do use those programs they have all pretty much told me that Quartus would be the best program for me since I don't want to learn an HDL. Quartus has a schematic entry interface like ispLever, but I had read that ispLever was going to get rid of theirs in the next version. So I'm pretty much stuck with Quartus I think.

I just spoke with a buddy of mine who is in school for electronics. I had been talking to him about this project as well off and on for the past few weeks. He said I may want to post the project on a freelance Site like GetAFreelancer.com in their electronics section. He said I should be able to find a programmer who would be willing to work on the project for just a few hundred since it's a really simple project.

Since we are all new to this it may be worth me posting the project ($10 and under) and finding a few guys to talk it over with and see what they think we would need and should do. Not that I don't think we could find a workable solution, but it may be a big time saver to talk it over with someone who has worked on different projects using PLDs, SDRAM and HDL software before.

Thoughts?

[Grant Stockly]

The problem with schematic entry in its purest form is that you have to make the entire design using logic chips. The Altera software has a schematic entry that allows you to design high level logic blocks in the HDL languages and draw schematic wires to and from the ports.

I'd like to learn one or the other, potentially VERY soon for the ramwall project. I'm split between Altera and Xilinx.

[rgjones]

I am pretty sure Xilinx ISE lets you do the same thing - your top level file can be schematic, it will make symbols from the input/output ports of your HDL and you can connect the dots so to speak

Not sure if your familiar with Andre' Lamothe from the www.xgamestation.com web site. He has done a lot of this stuff before. I know he has looked at the various IDE's and his recommendation is typically Lattice esp for beginners ... thats what he has used for several CPLD based products on his web site - ymmv

FYI for Xilinx digilent has videos for ISE and so does Tony Burch http://www.burched.com/index.php

I had a real problem with Quartus and their licensesing files - finally got it straightened out - I wanted to see Alex Freeds latest FPGApple in it's native environment and it looks to me on first blush that ISE and Quartus appear vary similar in their toolset.

Henry, I don't have a problem if you want to test the waters on GetAFreelancer.com

[rgjones]

So @ 60MHz you don't think the AVR32 would be fast enough to respond?

I havn't worked it out myself ...

I just got the http://www.atmel.com/dyn/products/to...p?tool_id=4114 board last week ... no time to goof around with it yet

[rgjones]

btw ... I was was pretty surprised when I looked around a few months ago and didn't find anyone offering a board like we are proposing - I found one link on the Sparkfun forums where one of their guys at the time proposed the idea but nothing ever came of it from them. I could not even find a breakout board with just the premounted SDRAM - although I did find one vendor who has one in the wings it's not yet avallable for sale.

Mounting just the TSOP II SDRAM shouldn't be a big deal

[Grant Stockly]

An 8bit AVR at 20MHz is too slow for a 2MHz 8080.

The AVR is fast enough, but it would require a CPLD.

I interfaced a SCENIX directly to the ISA bus once. It required external address decoding. I think I was running at either 1 or 8MHz bus speed, but with like 30 wait states, so I'm not sure what the "final" speed was.

The INSTANT the ISA would access the scenix, the scenix would ask for wait states. It was tough. The scenix was running at 50MHz. Probably not as efficient though.

A CPLD and an AVR is MORE than fast enough. Its not that the AVR wasn't fast enough to process the data, but that its not fast enough to read the address, figure out what goes where, return data, etc. Too much to think about in the 1us allowed.

[rgjones]

Originally Posted by Grant Stockly

A CPLD and an AVR is MORE than fast enough. Its not that the AVR wasn't fast enough to process the data, but that its not fast enough to read the address, figure out what goes where, return data, etc. Too much to think about in the 1us allowed.

Thats the conclusion Alex Freed came to when he used a 20MHz avr for his Psuedo disk project although I thought that at 60Mhz it might just be fast enough ....

I think I am going to hook my test board up to the Apple II bus anyway - a good excercise to get to know my Logic Analyzer

[Grant Stockly]

What Logic Analyzer do you have? The DigiView?

[rgjones]

Originally Posted by rgjones

So @ 60MHz you don't think the AVR32 would be fast enough to respond?

I havn't worked it out myself ...

I just got the http://www.atmel.com/dyn/products/to...p?tool_id=4114 board last week ... no time to goof around with it yet

Just looking at this AVR32 board now and while it's wonderfull they brought out all the i/o onto two rows down the side of the PCB but did they have to make the spacing so frickin small? for want of another .5" of PCB they could have had a nice area to attach a standard breakout header.....

What are these people thinking of when they make these things?

[rgjones]

I am not sure if this is the norm in the electronics business but I have been waiting for quotes on a few things now and while it is small volume it really can't be that diffiicult if your setup for this business to give a quote on an assembly job ... do I really want to give my business to anyone that can't get a quote back in a reasonable time frame?