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  #21  
Old 04-21-2008, 02:21 AM
rgjones rgjones is offline
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I have been looking at this chip -MT48LC16M8A2 (http://download.micron.com/pdf/datas.../128MSDRAM.pdf) or this one MT48LC4M32B2 (http://download.micron.com/pdf/datas...MbSDRAMx32.pdf)

It really depends on what the IP Core has been setup to work with - some need code changes and others just take parameters when you build the HDL.

I like the idea of using the MT48LC16M8A2 chip as the datapath is 8 bit wide
and it help reduces the pin count over the 32 bit wide memory but most IP cores seem to be setup for 16 or 32 bit accesses.

Are you guys more partial to verilog or VHDL? I have been trying to learn Verilog.

Most FPGA/CPLD chip vendors have Sample SDRAM controllers - some have restrictions in that you may only use their IP on their specific chips -There are also a few free open cores out there - one in particualr that I started to work with is http://www.cmosexod.com/sdram.html. Latticealso seems to have some good cores which fit in a cpld ... I found not all cores are created equal when it comes to resources taken to get the job done.

Last edited by rgjones; 04-21-2008 at 02:31 AM.
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  #22  
Old 04-21-2008, 03:06 AM
Grant Stockly Grant Stockly is offline
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I bet you Apple II guys could use that SDRAM with only 2 gals or a small CPLD. Just put the chip into self refresh mode between reads/writes. That wouldn't work for an Altair, since it can run without a clock.

I remember looking at this chip too. I think for me the best solution is using 16 of the $10 chips to get 16MB. My customers won't care and they will appreciate a board full of 32 pin DIPS more than some small finger nail sized thing.
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  #23  
Old 04-21-2008, 04:12 AM
Reactive Reactive is offline
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Glenn: I would tend to agree with the MT48LC16M8A2 is the way to go. I also think Grant is right about only needing some small logic to address the IC. The SDRAM looks pretty basic too. There's some odd requirements to it's startup though which I'd have to think about, but I don't think it's a bad choice for what we want to use it for.

It's 3.3v, so we'd need some level translation obviously. I count 29 lines we will need to interface with. May be one or two that aren't need as I have just skimmed the data sheet at this point. So a GAL would work for addressing and refresh (the thing does CBR 'standard' rate it looks like) but not level translation unless there's some new ICs I don't know about. So a small CPLD would probably be our best choice, but I'd have to do a bit of research to tell for sure.

TSOP is good as I can solder that and we can also find DIP adapters pretty cheaply for prototyping.

I have Quartus but haven't really played around with it too much. I liked it because it had a schematic entry feature for design. No need to learn an HDL if you didn't want to. Altera also offers a pretty decent selection of parts. They also offer what they call 'Certified Design Centers' to help with different projects. I'll get on the phone with them and see if I can't find what part they would recommend and possibly talk with one of their Certified Design Centers and see what kind of price they would charge for creating the HDL program for us. If it's only a few hundred dollars then I say we let them do it and split the costs. That would save us a lot of time and in reality the program really shouldn't be that hard to create. Once we have a working model to work with we could modify the code as needed for other things. But at least we would have an example rather then starting from scratch and trying to learn everything at once.

Thoughts/ideas?

I'll post what I find here.

Grant: Why wouldn't this work for you? I don't follow.

PS - Grant: Can others see this Forum as well? I don't really care but if I send someone here I just want to know that they can see everything and follow along.
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  #24  
Old 04-21-2008, 04:54 AM
Grant Stockly Grant Stockly is offline
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Right now only two people are allowed to see this section.

What I could do is make it invisible to EVERYONE, including you and Glenn. Then anyone who knows the URL would be able to see it. Would you like that?

In the end it would be more economical to use a CPLD. A more "proper" controller could be made AND some CPLDs will run on 3.3v yet still have 5v tollerant I/O (most chips don't allow inputs above +.3v VCC or so).

Since we're dealing with LS and HC TTL 3.3v logic will work just fine.

The Altair can run with the clock stopped. If you were to look at the memory chips, the read line is held low as long as the computer is stopped. If you "view" memory location 0xA5FB, then the address lines have 0xA5FB and the read line STAYS low. Same thing with any front panel setup.

There are some TTL dram controllers for the Altair, but a 3.3v CPLD with 5v logic kills two birds with one stone, and cheaply.
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  #25  
Old 04-21-2008, 02:21 PM
rgjones rgjones is offline
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FYI - when talking to chip vendors

SDRAM is now considered old Skool by most chip vendors having come out in the later 90's - most of the IP is dated from around that time as well ... not saying it isn't useful but most chip vendors are now pushing DDR2 and DDR3 designs for which we have no use.

btw we need logic for two functions - one part is to control the SDRAM chip and the other part is what I call the personality module - the logic that talks too and possibily emualtes older style ram. This gets closer to how this module is being implemeted in a system and i see both parts of the required logic residing in the same CPLD.
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  #26  
Old 04-21-2008, 02:27 PM
rgjones rgjones is offline
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Guys this is a blurb I put together to ask the opinion of this project from a few other folks awhile back

------------------------------------------------

I am considering making a cheap 8bit RAM card.

While my initial goal is to make a logical 16MB Slinky and or Ramworks III clone card I feel it could also be useful for other 8 bit platforms like AVR and PIC

My preferrred approach would be to use a small FPGA/CPLD (Xilinx XC3S100E or equiv ) mated with cheap SDRAM (non DDR).

The alternate approach is to use an ARM9 processor or AVR32 (vs FPGA) that already has a built-in SDRAM controller..

Do you see any major draw backs in either high level approach? I haven't really thought through the ARM9 approach very far but I think it should be doable. It would end up being more software driven vs hardware (verilog) but in the end probably more expensive to produce.



Here are some further details about the FPGA approach


I see this module in 3 logical parts in one FPGA

SDRAM Controller core
Std interface
Host interface


*SDRAM Controller IP*

There are a dozen or so SDRAM (non DDR) controllers out there from various chip vendors, 3rd party and open cores. One I found that I was going to base my project on was http://www.cmosexod.com/sdram.html - this seem to have good documentation for a noob like me and it's configurable for 32, 16. or 8 bit accesses. The downside is it also is configured for 32 bit wide memories (to give the flexibility of course). My first thought was to use this core and hardwire it to a chip like MT48LC16M8A2 to achieve two goals - 1) reduced logic required (to possibly fit in a CPLD vs FPGA) and 2) reduce the i/o required to get a small a pin package as possible or the other option is to just leave the core as is and use 32 bit wide memory.

I also just saw some controller IP on the lattice web site that looks like it is usable in small devices but I have not had time to review it yet.

**Standard interface (optional but I like the idea)* *

This would take the form of a sram "like" interface that would provide 24 bits address to the SDRAM controller module, provide what ever size data bus the SDRAM controller required. This interface is strictly internal only to the module. It would most likely be synchronous to the SDRAM controller and it would need to implement what ever control signals the SDRAM controller core required as well as take the input from the host interface IP. it also needs to handle the SDRAM clock and the host clock.

*Host interface*

Remaining available logic and i/o should be available to implement the host specific **personality** module. This could take the form of a simple sram like interface (preferably with zero wait state) or it could mimic an old dram (cas/ras interface). it would be up to the module to implement but it would talk to the standard interface the same way regardless of how it talked to the host. Since the connecting system typically will have a much slower clock then the sdram, zero wait state (from the host perspective) should be possible. The databus would only be 8 bits wide at this point.

The host logic needs to be 5v tolerant but everything else would/should be 3.3v


-------------------------------

Comments?
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  #27  
Old 04-21-2008, 02:33 PM
rgjones rgjones is offline
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When you reading the note above you are probably wondering why I am mentiong FPGA vs CPLD etc ...

1) available logic
2) number of avaialble i/o's
3) $$$

some desgins I looked at from xilinx for example wouldn't even fit in the largest CPLD availalbe and even if they did they were way more expensive then the small fpga (logic slice)

anyway thats the designers job ...find the best device to fit the application ...

)
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  #28  
Old 04-21-2008, 04:11 PM
Grant Stockly Grant Stockly is offline
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Quote:
Originally Posted by rgjones View Post
Guys this is a blurb I put together to ask the opinion of this project from a few other folks awhile back

------------------------------------------------

I am considering making a cheap 8bit RAM card.

While my initial goal is to make a logical 16MB Slinky and or Ramworks III clone card I feel it could also be useful for other 8 bit platforms like AVR and PIC

My preferrred approach would be to use a small FPGA/CPLD (Xilinx XC3S100E or equiv ) mated with cheap SDRAM (non DDR).

The alternate approach is to use an ARM9 processor or AVR32 (vs FPGA) that already has a built-in SDRAM controller..

Comments?

Use hardware for hardware solutions. The AVR32 is pretty big too.
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  #29  
Old 04-21-2008, 05:11 PM
rgjones rgjones is offline
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Pretty big in what way?

AT32UC3A0512 - 32-bit Flash Microcontroller based on AVR32 UC core featuring 512K bytes Flash, 64 KBytes SRAM, 10/100 Ethernet MAC, full-speed (12 Mbps) USB 2.0 with On-The-Go (OTG) capability.

The AT32UC3A0512 also feature SRAM/SDRAM external bus interface.
The AT32UC3A devices deliver 80 Dhrystone MIPS (DMIPS) at 66 MHz and consume only 40 mA at 3.3V.

All in a LQFP144 - 20x20 mm package (same as that xilinx breakout board I already have) - 109 - 5v tolerant i/o pins

Actually the AVR32 would make the basis of a very nice co-processor card - the ram interface card could be the first option for it.


Well it's an option
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  #30  
Old 04-21-2008, 05:21 PM
rgjones rgjones is offline
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The main players are

Actel
Altera
Lattice
Xilinx


Henry, have a look at Lattice vs Altera or Xilinx - download the ispLever developement platform and have a look.

It is supposed to be easier to use vs Altera or Xilinx

Grant, who is your preferred chip vendor?

Last edited by rgjones; 04-21-2008 at 06:05 PM.
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