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Old 12-29-2008, 01:56 PM
Reactive Reactive is offline
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Default DRAM to SD-RAM Adapter

Well, it's be a while. I've been busy with 'real' (boring) work. A buddy of mine called in mid-September and offered me some holiday money type work. Turns out it may be more of a full time job when all is said and done. I'm now booked till the end of February, with the possibility of full time employment. I do miss my free time though.

Anyway, the place I work at does VHDL and IC design. So I've met some people who seem to be willing to look at that old VHDL code we found and modify it to work with whatever SD-RAM we choose. My idea was to select several SD-RAM modules and have code written to support them all. This will give us some examples of what and where the code would need to be changed in the future should our choices of SD-RAM module change.

My idea is to create a PCB that has a CPLD, JTAG header, Voltage Regulator, and several SD-RAM SMT areas so we can mount several different ones for testing. I've found some older 16 and 32 Meg ICs I think would be worth testing.

I then think it would be a good idea to hardwire (trace) in the Voltage and Grounds, but use Vias with Machine Pin SIP headers to surround the CPLD and SD-RAM ICs. That way we can use Fly Wires and change things as needed. Other ideas would also be welcome!

I'll post a pic of the PCB for everyone to check out and approve. I'll then order a few for us to tinker with. I'll also order the ICs and mount everything. I even have some JTAG Programmers for the CPLD if anyone needs to borrow one.

My idea with testing and the VHDL code is to allow us to directly wire in the test SD-RAM module to a RAMWorks or RAMFactor card and use their test programs to test a range of RAM, say one Meg at a time. Then using a jumper wire set each Meg on the SD-RAM to test with. This will save a bit of time I think by testing only 1 Meg, but we could also wire in more Megs to test at the added cost of more Fly Wires and time. Of course it's just a start as someone like Glenn would still need to take the code and customize it for his own use since you could save CPLD space with using less address translation.

Just some ideas I had. Any suggestions would be appreciated. I'll be in touch as soon as I have some pics.
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Old 01-06-2009, 03:31 AM
Reactive Reactive is offline
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Default SD-RAM Project PCB

I'm back!

Think I'm done. Here's what I have so far:



First thing you might notice is everything is duplicated. Not so actually. There is room for two of everything, but actually different items.

CPLD: Xilinx XC95144 and Lattice ispLSI 2064
Why Lattice you ask? I got a deal on several hundred units. They will work for what we want, so let's use them! I'll still get code written for the Xilinx though.

Two Voltage Regulators (SOT23-5 - far left area) are for 3.3v and 2.5v. For CPLD and RAM.

The RAMs are Digi-Key PN: 557-1218-1-ND and 557-1176-1-ND. 128MB and 512MB. The code should be about the same, so I might as well have then write it for both. I also plan on selling these units as modules/kits for others to use as DRAM replacements, so it just makes sense (I think).

The SIPs are going to be Machine Pin Headers. We can then use Bell Wire to connect everything like a mini-breadboard.

So... thoughts? Ideas? Suggestions?


Henry
ReactiveMicro.com
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Old 01-08-2009, 02:26 AM
Grant Stockly Grant Stockly is offline
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I would fill in all of the unused space with .1 spaced vias, pad per hole, like bread board.
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Old 01-14-2009, 01:59 AM
Reactive Reactive is offline
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Default Breadboard area

Yeah, I guess a little Breadboard area in the unused space is a good idea. Can't hurt at least and won't cost any extra.

On a separate topic - I was going through the different modes I'd like to have this Adapter support and started compiling a list.

I/Os required for JUST DRAM Emulation - List of possible modes to support.

256k x 1bit DRAM:
A0 to A9, /WE, /RAS, /CAS, D, Q = 15 per IC, 29 per bank.
Notes: All address lines are tied together for all banks.
/RAS and /CAS are tied together per bank.
8 bits (Din/Qout) per bank - Each bit from each bank is tied together. i.e.: D0's are all tied together, etc.
/WE are all tied together for all banks.


256k x 4bit DRAM:


256k 30 Pin SIMM (No Parity): Need datasheet.


256k 30 Pin SIMM (Parity): Need datasheet.


1Meg x 1bit DRAM:
A0 to A9, /WE, /RAS, /CAS, D, Q = 15 per IC, 29 per bank.
Notes: All address lines are tied together for all banks.
/RAS and /CAS are tied together per bank.
8 bits (Din/Qout) per bank - Each bit from each bank is tied together. i.e.: D0's are all tied together, etc.
/WE are all tied together for all banks.


1Meg x 4bit DRAM:
A0 to A9, /WE, /RAS, /CAS, /OE, DQ0-3 = 17 per IC, 21 per bank.
Notes: All address lines are tied together for all banks.
/RAS and /CAS are tied together per bank.
8 bits (DQ's) per bank - Each bit from each bank is tied together. i.e.: DQ0's are all tied together, etc.
/WE are all tied together for all banks.
/OE are all tied together for all banks and grounded.


4Meg x 1bit DRAM:


4Meg x 4bit DRAM:


1Meg 30 Pin SIMM (No Parity):
A0 to A11, /WE, /RAS, /CAS, DQ0-7 = 23 per SIMM.
Notes: All address lines are tied together for all SIMMs.
8 bits (DQ's) per SIMM - Each bit from each SIMM is tied together. i.e.: DQ0's are all tied together, etc.
/WE are all tied together for all banks.


1Meg 30 Pin SIMM (Parity):
A0 to A11, /WE, /RAS, /CAS, IP, OP, /CAS, DQ0-7 = 26 per SIMM.


4Meg 30 Pin SIMM (No Parity): Need datasheet.


4Meg 30 Pin SIMM (Parity): Need datasheet.


16Meg 30 Pin SIMM (No Parity): Need datasheet.


16Meg 30 Pin SIMM (No Parity): Need datasheet.



Anyone (Grant?) have any other modes they would like to see supported? I just start 'basic' and add support as I can find people to test the other modes. I know some are PC only, for instance.

I'm also looking for those datasheets listed above. Anyone know where I can find them?

Comments/suggestions?
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