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  #61  
Old 05-02-2008, 05:09 AM
rgjones rgjones is offline
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Originally Posted by Reactive View Post
Wow, that is really coming along. What size are those Caps/Resistors? 805?

That's looking really good!
They are 201's - itsy bitsy tiny weeny

remember it's only 1.5" x 1.5" in total size

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  #62  
Old 05-02-2008, 06:05 AM
Reactive Reactive is offline
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Originally Posted by rgjones View Post
They are 201's - itsy bitsy tiny weeny

remember it's only 1.5" x 1.5" in total size

Oh geeze! 201s?!?! Now that IS small. I see I'm going to need a new set of tweezers. ;-)

You may want to change them to 805s. They are small, but at least workable - IF you have a good eye and iron. Of course if you have them built then who cares?
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  #63  
Old 05-02-2008, 07:01 AM
Reactive Reactive is offline
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Originally Posted by rgjones View Post
Theorectically a CPLD in either case will require the same amount of i/o. The option with SDRAM will require a larger CPLD from a logic cell point of view as we need to handle the SDRAM controller + any host logic whereas the CPLD for a PSRAM only needs to handle the host logic for the most part.
True. The CPLD for the PSRAM should be able to be smaller then for the SDRAM. That being said, most small CPLDs are under $3. I have no idea what actual size we will need though. Maybe you guys can download those SDRAM CPLD program images and see what size CPLD they will fit in to (since I have less knowledge in that department). Then maybe we can get a better idea if a 72 cell CPLD is a good choice to start to price with. For the same pins and just a little more price we can also go with the 144 cell CPLD. The XC95 series also goes up to QFP208 with 192 I/Os and 288 cells at roughly $15. So we have some options open to us on how crazy we can go if needed or if we want to offer a larger amount of support.


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I find myself flip/flopping back an forth between the two options ... Damn Micron for not offering the PSRAM in tsop II 54.
I here you there. Just stupid if you ask me, but then again I think everything is just going BGA so why produce a legacy item if it's not going to be used? I bet everyone else is cheering them for going BGA. ;-)


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Originally Posted by rgjones View Post
There were two approachs to take with the code - a) use it as is but that means using 32 bit wide memory which means a 86 pin tsop II. Make small adjustment to handle 16MB vs 8MB or b) modify it to use the 8bit wide memory and also handle 16MB vs 8MB.
Very true. I don't even think I would matter actually other then for our sake of keeping things straight program wise. It does look like that 8 bit wide access would require less I/Os though. Only from what stand point does it seem worth redoing the code.


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Originally Posted by rgjones View Post
Wouldn't you just use a bank register in the cpld vs using i/o lines? Hmm this also really depends on the application ... for a slinky for example you only need d0..D7, r/w, devsel, a0,a1, maybe ph0, res.
As far as using a Bank Register, I assume IN the CPLD that's what would happen but from the Apple II side, coming from a 'raw' card like the RAMWorks III we would need to deal with some kind of Bank input. My idea was also to offer some replacement for DRAM and SIMMs so legacy users could wire in this module in to existing cards if they wished. It would be cheaper then buying DRAM at least. It would also allow people to prototype using old card designs like the Apple IIgs 1 Meg card to 4 Meg card conversion found here: http://www.apple2gs.republika.pl/eng.html

Just an idea of course. If there's the available I/O then I say we try to offer the Bank support too as an option.

Concerning the Slink addressing: D0..D7, R/W, DevSel, A0, A1, PH0, RES

Just A0 and A1? Nothing larger? Reset too? I don't I've seen that used on a Memory card before, or maybe I'm thinking of something else?

Either way we should have some I/Os left over using the XC9572. Can't hurt to wire some up and leave them as options that we and others can use for different projects. That is assuming we don't use up all the cells with the SDRAM program. As mentioned above we have some options when it comes to the CPLD if more I/Os are needed and the cost isn't that major of a factor.


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Originally Posted by rgjones View Post
My idea was to route any unused i/o pins to the out side of the adapter that way the CPLD programmer can do what they want.
Good one! Actually we could route all the I/Os to a break out section that users could wire in to if they wanted. Shouldn't add much more space to the PCB either. Maybe even bow tie some I/Os so they could cut and rewire as needed.


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Originally Posted by rgjones View Post
I still like the idea of a CPLD/RAM chip all on one SQUARE or DIP breakout board.
I'm all for DIP myself. It should be able to fit in a simple bread board or Little Proto II then. I'm looking around for blind pins now too. The other idea could be to use socket pins like I have on the Dual Adapters I sell and that way users could wire in to the top of the pins and insert the Adapter to a socket the from the bottom. The Adapter would then look something like this but without the ROM of course: http://www.reactivemicro.com/image/p...l-EF-Large.jpg

Weird. Is that pop up URL bocked for you too? If so just copy and paste the URL in to your address bar in your browser. Damn Hot Link protection seems to be over protecting me again. Need to add this address as 'Safe' I guess.


On a side note: If/when we release this project I was going to do some instructional videos on how to actually use the Xilinx software and the code. So as we figure out what the code is doing and why please document it in the code so I and others will have something to go on. Just be as basic and as descriptive as possible. The better things are documented the better our item will sell, or so I hope. And who knows? I may even be able to follow along too! ;-)
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  #64  
Old 05-03-2008, 07:57 PM
rgjones rgjones is offline
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Originally Posted by Reactive View Post
I here you there. Just stupid if you ask me, but then again I think everything is just going BGA so why produce a legacy item if it's not going to be used? I bet everyone else is cheering them for going BGA. ;-)
Did a little more research and there is a reason it's called CellularRam ...the real market for this stuff is Cell phones and not much else.

Quote:
Just an idea of course. If there's the available I/O then I say we try to offer the Bank support too as an option.
My understanding with both the slinky and the RWIII is that banking is handled with a 8 bit register.

Quote:
Concerning the Slink addressing: D0..D7, R/W, DevSel, A0, A1, PH0, RES

Just A0 and A1? Nothing larger?
Slinky uses a 4 i/o addresses - 3 bytes are address (only 20 bits are used for a total of 1MB) and 1 byte for data.

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Reset too? I don't I've seen that used on a Memory card before, or maybe I'm thinking of something else?
Put the card in a known state at power on
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  #65  
Old 05-10-2008, 06:40 PM
Reactive Reactive is offline
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Hey Guys.

Any headway in the SDRAM project? When I spoke to Grant he hasn't really done anything since he's busy at work on some other CPLD project.

So Glenn... anything?

I was going to post an RFQ on GetAFreelancer.com and see how many people would take the project for $250. Do you have a testing platform already setup? If so I could email code for testing as it comes in. I'd be more then willing to share code in lieu of some help testing it.

Of course if you're already working on something and don't think it's too far off before we have something to test with then I'll hold off a while longer. As I said before I'd much rather give you the cash then someone else.
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  #66  
Old 05-10-2008, 08:51 PM
rgjones rgjones is offline
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Originally Posted by Reactive View Post
Hey Guys.

Any headway in the SDRAM project? When I spoke to Grant he hasn't really done anything since he's busy at work on some other CPLD project.

So Glenn... anything?
No.... After i mounted the SDRAM chip ... I decided to go back and finish off the SRAM interface for the IIcmxp as I left it 80% wired up before I got derailed with pumping out uthernets and our discussion on SDRAM. Now that it's complete I seem to be struggling a bit to get it working properly. The simulation works ok but I can't get the SRAM address lines to drive using the actual hardware. Probably goofed on the wiring somewhere.

I would like to see that going sucessfully before I do any work on the sdram interface.

Quote:
I was going to post an RFQ on GetAFreelancer.com and see how many people would take the project for $250. Do you have a testing platform already setup? If so I could email code for testing as it comes in. I'd be more then willing to share code in lieu of some help testing it.

I may be able to start wiring that up next week. I will at least get the power and jtag going ... we will need to get a feel for pin placement before I can start to actually wire anything beyond that up.

Quote:
Of course if you're already working on something and don't think it's too far off before we have something to test with then I'll hold off a while longer. As I said before I'd much rather give you the cash then someone else.
Go for it an lets see if you get any action
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  #67  
Old 05-14-2008, 02:16 AM
Reactive Reactive is offline
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Hey Guys.

Quick note about 100 Pin QFPs - ALWAYS clean them after soldering! I had some odd issues that I just couldn't find. Seems some Brakleen (Pep Boys degreasor) and a toothbrush did the trick. I wash the PCB and CPLD and then brush each side of the CPLD pins twice. Then some compressed air to finish the job. The Brakleen evaporates and leave zero residue.

So make a note and add this procedure to all 100 QFPs you solder.
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