I have been looking at this chip -MT48LC16M8A2 (
http://download.micron.com/pdf/datas.../128MSDRAM.pdf) or this one MT48LC4M32B2 (
http://download.micron.com/pdf/datas...MbSDRAMx32.pdf)
It really depends on what the IP Core has been setup to work with - some need code changes and others just take parameters when you build the HDL.
I like the idea of using the MT48LC16M8A2 chip as the datapath is 8 bit wide
and it help reduces the pin count over the 32 bit wide memory but most IP cores seem to be setup for 16 or 32 bit accesses.
Are you guys more partial to verilog or VHDL? I have been trying to learn Verilog.
Most FPGA/CPLD chip vendors have Sample SDRAM controllers - some have restrictions in that you may only use their IP on their specific chips -There are also a few free open cores out there - one in particualr that I started to work with is
http://www.cmosexod.com/sdram.html. Latticealso seems to have some good cores which fit in a cpld ... I found not all cores are created equal when it comes to resources taken to get the job done.