http://vt100.net/mirror/harte/Cromem...ual%201983.pdf
There are a few 68000 boards out there for the S-100 bus.
I would probably bring the excess memory addresses and specific processor timing out to a header to connect to a memory or ROM board.
The RAM seen to the MITS bus would either be a window or simply 0-64k. I/O addresses would have to be decoded some how...
Its not too much of a serious project, but its nice to think about.
