[philrrtx]

After a few bumps and stops, I have the Processor Technology 3P+S I/O card working via an RS232 interface with an LSI ADM-3A CRT (a nice terminal contemporary to the Altair). Whoever had this card previously apparently didn't understand just how it worked, because s/he had installed a 7404 inverter chip in an (thoughtfully provided by PT) empty IC slot and had run the TBE (Transmit Buffer Empty) and RDA (Receive Data Available) signals from the UART through it before putting them on the data bus. This made them much more difficult to detect at the CPU (they show up as 0s instead of 1s).

I removed the inverters, after which the PT serial test code almost worked. It was supposed to output lines of characters from 30H to 55H, with or without a delay as determined by a sense switch. You could then set a different sense switch and it would jump to the input test, where it received characters and echoed them back to the interface. Yet a different switch indicated the test was over, resulting in a jump to a HLT. Mine would output one character, input one character, then halt. This was tracked to a failing read of the sense switches. They were all coming in as ONEs, no matter how they were set. When I replaced the sense switch reads with NOPs, the test code worked perfectly, and I could send and receive characters with the terminal.

Some scope probing today reveals that a 7404 inverter chip on the front panel control board appears to be bad; it isn't passing the SNSW read enable signal. I'll need to replace the chip to proceed any further.

BTW, I notice that the front panel control board relies on behavior that I couldn't find described anywhere in the 8080 documentation, and that is that the device address (the argument to an IN or OUT statement) gets sent out on both the high and low bytes of the address bus. The 3P+S I/O card, for example, looks for its address on A0-A7, but the logic for the sense switch read looks for 0FFH on A8-A15. Nothing I found in either the Altair or 8080 documentation states that this is the chip's normal behavior on I/O statements.