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Old 09-05-2005, 02:54 PM
Grant Stockly Grant Stockly is offline
Join Date: Jan 2005
Posts: 447

Article: 77967
Subject: Re: Microscope examination of a PLD
From: Tommy Thorn <foobar@nowhere.void>
Date: Mon, 24 Jan 2005 02:09:58 GMT
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logjam wrote:
> So I will try this on monday:
> -Shave PLD about 1/8"
> -place flat on a hot plate, around 130*C
> -Drip nitric acid on it until the silicon is visible
> If all else fails, I'm getting a 100MHz 18 channel 128k+ sample logic

Well, even if you get a visual reading of the bits, I would still want
to verify it by frobbing pins. However, rather than a logic analyzer,
why not simply hook it fully up to an FPGA? There are plenty < $500
boards out there that would be up for the job. That would give you all
the functionality of the LA with the additional ability to incrementally
build up and verify the reengineered model, all within the same framework.

Just an idea,
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