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Old 01-28-2008, 07:40 PM
Grant Stockly Grant Stockly is offline
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Join Date: Jan 2005
Posts: 447
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Code:
Name     Mini680 ;
PartNo   00 ;
Date     1/26/2008 ;
Revision 01 ;
Designer Grant Stockly ;
Company  Stockly Electronics ;
Assembly None ;
Location None ;
Device   G22V10 ;

/**** INPUT PINS ********************* DESCRIPTION *************************/
PIN   1 = CLK1                    ; /* Clock Phase 1                       */
PIN   2 = RWi                     ; /* R/W from Processor                  */
PIN   3 = VMA                     ; /* Valid Memory Address                */
PIN   4 = ADDRAND                 ; /* Output of BA0...7 NAND Gate         */
PIN   5 = HALT                    ; /* 1k memory low jumper (not used)     */
PIN   6 = CLK2                    ; /* Clock Phase 2                       */
PIN   7 = A10                     ; /* Buffered Address bit 10             */
PIN   8 = A11                     ; /* Buffered Address bit 11             */
PIN   9 = A12                     ; /* Buffered Address bit 12             */
PIN  10 = A13                     ; /* Buffered Address bit 13             */
PIN  11 = A14                     ; /* Buffered Address bit 14             */
PIN  13 = A15                     ; /* Buffered Address bit 15             */
/*** OUTPUT/INPUT PINS *************** DESCRIPTION *************************/
PIN  23 = BE                      ; /* Mini680 Data Buffer Enable          */
PIN  22 = RD                      ; /* Read Strobe for Flash and RAM       */
PIN  21 = WR                      ; /* Write Strobe for Flash and RAM      */
PIN  20 = FLASH_CS                ; /* Flash Memory Chip Select            */
PIN  19 = RAM_CS                  ; /* RAM Chip Select                     */
PIN  18 = PAGE                    ; /* Write Strobe to Page Register       */
PIN  17 = RWo                     ; /* R/W to Motherboard                  */
PIN  16 = NC                      ; /* No Connect (free output/input)      */
PIN  15 = A8                      ; /* Buffered Address bit 8              */
PIN  14 = A9                      ; /* Buffered Address bit 9              */
/***************************************************************************/

Field Address = [A15..8];

/***********************************************/
/***** Handle Front Panel Operation of RAM *****/
/***********************************************/
/*****************************************************************/
/* When HALT is low, RWo needs to be an input for writing to RAM */
/*****************************************************************/
RWo.OE = HALT;

/*************************************************************/
/***** Generate Read and Write Strobes for Flash and RAM *****/
/*************************************************************/
/******************************************************************/
/* RWi - R/W input from processor - HIGH=READ, LOW=WRITE          */
/* CLK2 is the synchronous bus clock and is active HIGH           */
/*      CLK2 must be high for a memory operation                  */
/* VMA indicates a stable and valid memory address is on the bus, */
/*      flash may require this                                    */
/* VMA is required for Flash and Page writes only                 */
/******************************************************************/
!RD = ((RWi & HALT) & CLK2)         /* Normal Operation RD Control */
    # (RWo & CLK2 & !HALT);         /* Front Panel RD Control */
                              /* Normal Operation WR Control */
!WR = ((!RWi & HALT) & CLK2 & ((VMA & !FLASH_CS) # !RAM_CS # !PAGE))
                              /* Front Panel WR Control */
    # (!RWo & CLK2 & ((VMA & !FLASH_CS) # !RAM_CS # !PAGE) & !HALT);

/*********************************************************/
/***** Generate Write Strobe for Flash Page Register *****/
/*********************************************************/
/*********************************************************************************/
/* Input ADDRAND is an 8 input NAND gate with A7-0 as inputs                     */
/* When [Address=C8xx] and [Address=xxFF] and [write] and [valid memory address] */
/*********************************************************************************/
!PAGE = Address:[C800] & !ADDRAND & !RWi & CLK2 & VMA;

/***************************************************/
/***** Generate Chip Selects for Flash and RAM *****/
/***************************************************/
/*****************************************************************/
/* RAM is from Address 0x0000 to 0x7FFF                          */
/* Space for optional internal RAM from Address 0x8000 to 0x87FF */
/* Flash is from Address 0x8800 to 0xC7FF                        */
/*****************************************************************/
!RAM_CS = !A15 ;

/* Flash is from Address 0x8800 to 0xC7FF */
!FLASH_CS = Address:[8800..C700];

/**********************************************/
/***** Generate R/W output to Motherboard *****/
/**********************************************/
/***************************************************************************/
/* When [RAM_CS] or [FLASH_CS] or [PAGE] (are addressed), make WRo low     */
/*      This is required to keep the motherboard data buffers in the WRITE */
/*      direction                                                          */
/* RWo needs to be LOW when accessing external memory                      */
/***************************************************************************/
RWo = (RAM_CS & FLASH_CS & PAGE) & RWi;

/***************************************************************/
/***** Generate direction output for Flash/RAM data buffer *****/
/***************************************************************/
/**************************************************************************/
/* BE MUST be high unless the 6800 is addressing and reading Flash or RAM */
/* When BE is high, the buffer is going from the 6800 to the memory chips */
/* BE needs to be HIGH when accessing external memory                     */
/**************************************************************************/
!BE = !(RAM_CS & FLASH_CS & PAGE) & !RD;

Last edited by Grant Stockly; 01-28-2008 at 07:42 PM.
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