Thread: Test Board
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Old 05-02-2008, 04:06 AM
rgjones rgjones is offline
Join Date: Feb 2005
Location: Ajax, Ontario, Canada
Posts: 44

Originally Posted by Reactive View Post
[GLENN: Did you use solder paste?]
Nope. Just heat.

Shoot! Okay, from every angle I look ANY Adapter + PSRAM is going to cost more then the SDRAM.
True BGA anything in small qty - very $$$ - only starts to get reasonable @ 100+

[The only 'advantage' to the PSRAM that I can see is no initialization and refresh generation will be needed. The main 'disadvantage' for the SDRAM is we will need to prefect some code to account for initialization and refresh generation. With either IC we will need some address translation.
From what I understand PSRAM is essentialy some logic fronting SDRAM in a super small package.
Theorectically a CPLD in either case will require the same amount of i/o. The option with SDRAM will require a larger CPLD from a logic cell point of view as we need to handle the SDRAM controller + any host logic whereas the CPLD for a PSRAM only needs to handle the host logic for the most part.

I find myself flip/flopping back an forth between the two options ... Damn Micron for not offering the PSRAM in tsop II 54.

I reviewed this site you found:

After talking with Grant he feels that we (as in you two) should be able to compare the difference between the and files and from that figure out the rest of the code by trial and error. I'm no programmer, and would have even less clue when it comes to VHDL, so I doubt I'd be much help in figuring out anything that could help or be of any real use. Although I could follow along with the code, say if we all do a three way voice chat in Skype. Maybe then I'll start to clue in on what's what. We would also need a proto Adapter which is where I may come in.
There were two approachs to take with the code - a) use it as is but that means using 32 bit wide memory which means a 86 pin tsop II. Make small adjustment to handle 16MB vs 8MB or b) modify it to use the 8bit wide memory and also handle 16MB vs 8MB.

So with this I think the MT48LC16M8A2 SDRAM and a CPLD is the way to go. Now this begs the question exactly WHICH CPLD we will need.

#1 - I assume we are going to go Xilinx for the CPLD. So we all should download the newest version of the WebPack Tools and also the Service Pack update. I think Grant has already done this. I still need too. This way we can all share files.
I think I am up todate

#2 - The SDRAM IC: MT48LC16M8A2. I have found several parts on DigiKey's Site. PN: 557-1069-1-ND, 557-1070-1-ND and 557-1218-1-ND. They range from $7.49 to $5.44. I have no idea the difference between the part numbers. Anyone know? I was going to order a few for testing and just want to make sure I have the correct ones. Glenn: Which one did you order?
one part is industrial (temp grade), the other two are commercial. Of the two commercial ones, one is lead free and the other is not - same price. I ordered 557-1218-1-ND

#3 - Which CPLD will we need? I have a few XC9572s on hand. I'd be more then willing to share them as needed, if they will help. Which now begs the question of EXACTLY how many I/Os do we need to deal with?
I can use the XC9572XL or XC95144XL I have

Looking at the SDRAM Data Sheet I count 8 DQ lines. (16x8 mode of course)

I then see WE, CAS and RAS. So that's now 11 I/Os.

I believe that CS can just be tied LOW. Anyone see something different? Still 11 I/Os if so.

BA0 and BA1. So that's now 13 I/Os.

A0 to A11. So that's now 25 I/Os.

I believe that we only need 25 I/Os just to deal with the SDRAM IC. Anyone come up with something different?
I think you got it ... need to go back and look at it again

Now we will need to deal with the Apple II/Altair side. 8 DQs of course. And 0-7 to 0-9 for Address depending on the DRAM/Banking we need to emulate. For most of my needs 1 Meg Banks are it, although some 256k stuff also. Glenn's needs are probably the same. I'm not sure about Grant's. So that's a total of 18 I/Os. Anyone come up with something different?

I also think we will need some addressing as to the Banks as well. Like on the RAMWorks III card there are 4 banks of 256k. So we will need a way to interface with the Bank Addressing as well. 16 Banks would be 4 more I/Os. If we do emulate 256k then we'll need 32 Banks for 5 I/Os. So 5 it is?
Wouldn't you just use a bank register in the cpld vs using i/o lines?

Hmm this also really depends on the application ... for a slinky for example you only need d0..D7, r/w, devsel, a0,a1, maybe ph0, res

My idea was to route any unused i/o pins to the out side of the adapter that way the CPLD programmer can do what they want

So I count a grand total of at least 48 I/Os we need to deal with unless I'm overlooking something. The XC9572 should be fine at 72 I/Os and leave us with some pretty good expandability or possibility, like to emulate 16k DRAMs Bank wise. DigiKey #122-1386-ND. Price $2.58. 100 Pin QFP, which I can solder pretty well.

A total cost of $8.02 plus shipping (if the SDRAM price is $5.44). Not bad really.

Now we will need a test platform for the CPLD. Grant has this:
I have one as well

Not sure if this will work since the XC9572XL they use has only 44 I/Os. So it may be in our best interest to either find a similar trainer but with a larger I/Oed CPLD like the one we pick to work with or just create out own PCBs that I'll layout and solder up for us. With the custom PCB or Trainer we should be able to interface the SDRAM with say a RAMWorks card and have all 1 Meg reside on the SDRAM IC with just a few Fly Wires. This would be a good test I think. I also have a DRAM Tester that I could use to test the SDRAM in 1 Meg banks as well. I would have to manually wire the Address lines though. No major deal I think for test purposes.
I still like the idea of a CPLD/RAM chip all on one SQUARE or DIP breakout board.

Then there's the business end of selling the Adapters. Since Grant and Glenn wold be creating the code, you guys should get around 80% of the profits. I could design the Adapter layout, build them and supply prototypes for all our testing. Something around 20% of the sales profit for those efforts would be nice. I assumed we could use the design and code for our own projects free of charge, although I think I should still pay a licensee fee of around $8 up to the first 100 units since I really won't be doing the majority of the work. A PCB should be around $5 or less, parts would be about $10, and labor to build and test would be $10. I could build the Adapter as well for $10, but we may get a better price else where. The only disadvantage to going else where is that we would have to putout cash to have them built in bulk. Also if one of you guys wants the build/test free you could also build a few and make a few bucks that way as well. I'm pretty much setup for assembly so I just assumed I would build them and stock parts. So the Adapter would be about $25 our cost. We sell them for something like $40 each and Grant/Glenn get $6 each and I get $2 (plus the assembly/test fee of $10). You guys also spit the $8 licensing fee I would be paying.

Some numbers around there would probably work. I can't really see the Adapter being a huge seller, but at least you guys would get something for your time writing code. Depending on how things work out we may even be able to offer code for other specific systems which would enhance market appeal.

I also don't know how much work is going to be needed in customizing the code. So if it's only a couple hours and say Glenn does most of the work then we would want to adjust the splits accordingly. At least you guys will make a few bucks for your efforts from me. I also think we should make the source code open so others can use it. It may also be required if you use the code from that Site.

So that's where my heads at. Thoughts/ideas?
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