Guys this is a blurb I put together to ask the opinion of this project from a few other folks awhile back
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I am considering making a cheap 8bit RAM card.
While my initial goal is to make a logical 16MB Slinky and or Ramworks III clone card I feel it could also be useful for other 8 bit platforms like AVR and PIC
My preferrred approach would be to use a small FPGA/CPLD (Xilinx XC3S100E or equiv ) mated with cheap SDRAM (non DDR).
The alternate approach is to use an ARM9 processor or AVR32 (vs FPGA) that already has a built-in SDRAM controller..
Do you see any major draw backs in either high level approach? I haven't really thought through the ARM9 approach very far but I think it should be doable. It would end up being more software driven vs hardware (verilog) but in the end probably more expensive to produce.
Here are some further details about the FPGA approach
I see this module in 3 logical parts in one FPGA
SDRAM Controller core
Std interface
Host interface
*SDRAM Controller IP*
There are a dozen or so SDRAM (non DDR) controllers out there from various chip vendors, 3rd party and open cores. One I found that I was going to base my project on was
http://www.cmosexod.com/sdram.html - this seem to have good documentation for a noob like me and it's configurable for 32, 16. or 8 bit accesses. The downside is it also is configured for 32 bit wide memories (to give the flexibility of course). My first thought was to use this core and hardwire it to a chip like MT48LC16M8A2 to achieve two goals - 1) reduced logic required (to possibly fit in a CPLD vs FPGA) and 2) reduce the i/o required to get a small a pin package as possible or the other option is to just leave the core as is and use 32 bit wide memory.
I also just saw some controller IP on the lattice web site that looks like it is usable in small devices but I have not had time to review it yet.
**Standard interface (optional but I like the idea)* *
This would take the form of a sram "like" interface that would provide 24 bits address to the SDRAM controller module, provide what ever size data bus the SDRAM controller required. This interface is strictly internal only to the module. It would most likely be synchronous to the SDRAM controller and it would need to implement what ever control signals the SDRAM controller core required as well as take the input from the host interface IP. it also needs to handle the SDRAM clock and the host clock.
*Host interface*
Remaining available logic and i/o should be available to implement the host specific **personality** module. This could take the form of a simple sram like interface (preferably with zero wait state) or it could mimic an old dram (cas/ras interface). it would be up to the module to implement but it would talk to the standard interface the same way regardless of how it talked to the host. Since the connecting system typically will have a much slower clock then the sdram, zero wait state (from the host perspective) should be possible. The databus would only be 8 bits wide at this point.
The host logic needs to be 5v tolerant but everything else would/should be 3.3v
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Comments?