Test Board
 

I don't know if this chip is a good idea. Its just too small. The trace and space is TINY. I think since it will require a CPLD, it would be better to write a refresh block and use cheap LARGE DRAMs.

http://www.stockly.com/images4/08041..._schematic.jpg

http://www.stockly.com/images4/080419-PSRAM_PCB.jpg

Hey Grant.

You use WinQ CAD? What size traces did you use? 8 mil is about as small as we can go without getting a price penalty.

After actually seeing that pic we may be forced to go 4 or even 5 layer, without Ground or Power plain.


Henry

Trace width costs
 

Given the .75mm ball spacing

Gold Phoenix for example charges

155 Sq inch
2 layer base cost $99
6mil/5mil/4mil trace width/ clearance(2layers) $20/$40/$60

4 layer base cost $330
6mil/5mil/4mil trace width/ clearance(4layers) $40/$80/$200

If our breakout board was 4 sq inches for example that would yield about 38 peices so below is the cost per piece for reference

Trace widths
8 6 5 4
2 layer 2.55 3.07 3.58 4.10
4 layer 8.51 9.54 10.58 13.67


Since I have ordered with them before I might be ablet to get another 10% off

Yikes! Now I see why those VFBGA Adapters quoted from Aries are so much.

Grant: What are the clearances on your design? I also assume that pic is two layers? Give me some GERBER files and I can get some price quotes. Can you also post a pic of a blow up on the PSRAM area so I can get an idea as to the trace spacing and layout?

Glenn: I've been using QualityPCB.com. They have had the best prices for 2 layer stuff that James and I have found.

I just ran through the quote system for a panel the same size as GP and it came out to $130 and then they will add shipping to that. and it seems I have to panelize the board myself.

GP is $99, they panelize the board if it is repeat of same pcb and it includes shipping

You might want to give them a try - http://www.goldphoenixpcb.biz/special_price.php

Tell Shane that Glenn from a2retrosystems sent you .... :o)

Hey Glenn.

Thanks for the info. I do have one design I need quoted right now. I'll email him and see what prices he gives me.

I know I asked them for a quote just about a month ago and they were a bit higher. Think James had the same experience too. Maybe it's just the little panel stuff they have the best price with. Hard to say as it seems some guys specialize in one thing, yet others give better prices on something else.

I'll post the prices here and let you know who I went with.

Yeah ... my board is square so the yeild is likely higher giving a better price. Doesn't hurt to shop around.

Hmm actually for 1 panel GP is cheaper but @ 2 panels QualityPCB does come in %25 cheaper .. I will certainly get them to quote for me next time.

Thanks for the pointer Henry

The board I made was just a quick and dirty 30x2 .6" wide DIP adaptor.

The trace/space was 5mil. At 6.25mil it would end with 28 traces unrouted, 5 mil would route almost immediately. The board was 4 layer as shown.

The price penalty of using PSRAM might not be worth it. SDRAM would be harder, but pay for itself in the end.

A lot of the commercial designs out there are able to use 6 layers on small embedded boards.

Humm.... I would tend to agree from what I'm seeing in the prices. Not that anything HAS to be this PSRAMs of course.

Now back to square one. Anyone have a high density SDRAM IC in mind? TTSOP I would assume?

I bet we can even find a stock Adapter too then.

Why would we need an adapter for a TSSOP?

A 'stock' adapter for proto typing. Why produce custom PCBs until we get a known working unit? A simple SOIC to DIP adapter is all that's needed to work on a bread board for instance and MUCH cheaper.

Maybe even a PLCC to DIP adapter also for the CPLD. Then all custom surface mount for the production PCB.

I guess I was thinking we'd use a TFQP CPLD...

I guess I have a different opinion, since 3 overtime hours would pay for the prototype and I couldn't wire a bread board in 3 hours. :)

True, wiring a bread board would take some time but do you really think it's a good idea to produce a PCB without any testing first? I could just see a $150-ish expense for PCBs that don't work and then we still need to fight wiring and soldering which would now take even longer. I just normally get something on the bench working first, then start to translate the breadboard to CAD or schematic. Or am I making this a bigger production then it needs to be? It is really small and should be pretty simple I would assume. I guess what I'm asking is do you guys feel confident as creating PCBs without any testing first? I'm all for it then. I just know what happens when I don't do any testing - I end up having really cool but expensive PCB coasters for my desk. ;-)

I do like TQFP though! I just assumed PLCC for wiring convenience.

Sure. I just had a run of 10 PCBs which required 3 jumper wire fixes. Two were due to not proof reading a schematic. It wouldn't have mattered at all but two address lines were switched on a flash chip. That messed up the "knock-knock" sequence used to unlock the flash for writing. The other jumper wire was to add something that I didn't think of when I ordered it. :)

BUT, since it was a run of 10 I saved $150 or so against a prototype...so I guess it depends...

Three wires isn't too bad. It could just be a real pain to fix or rewire a proto PCB with all SMT compared to bread board. Of course a proto without a solder mask would probably be a good way to go just in case a rewire or jumper is needed. I always forget the mask is an option. ;-)

When I was testing one of my boards I found out DigiKey sent me the wrong parts. So I had to use a DIP version. Check out what I had to do. :)

http://www.stockly.com/images4/08012..._Hack_3814.jpg

Oh geeze! Yeah, that's exactly what I'm hoping to avoid. All in all, that's not too bad though. Don't you just love Bell Wire? ;-) I use it all the time too.

Anyway, you're call I guess. If you guys feel that it's a simple enough project where starting with a PCB is a good idea then I'm with you. I've just been there were I need to change the wiring and have to cut and wire traces. With 12 mil tracks it's not too bad, just a pain. 8s get a little hairy though.

http://www.solder.net/services/estimate.asp

using their estimator - they charge $11.25 per mounted BGA device whch is the best I have seen so far - just surfing the web.

Interesting Powerpoint presentation on BGA's

http://www.pcblibraries.com/download...ions%20PPT.pdf

also

http://www.adcom.co.il/pcb%20layout/..._Placement.pdf

So anyone have an idea as to a specific SDRAM IC to use?

I have been looking at this chip -MT48LC16M8A2 (http://download.micron.com/pdf/datas.../128MSDRAM.pdf) or this one MT48LC4M32B2 (http://download.micron.com/pdf/datas...MbSDRAMx32.pdf)

It really depends on what the IP Core has been setup to work with - some need code changes and others just take parameters when you build the HDL.

I like the idea of using the MT48LC16M8A2 chip as the datapath is 8 bit wide
and it help reduces the pin count over the 32 bit wide memory but most IP cores seem to be setup for 16 or 32 bit accesses.

Are you guys more partial to verilog or VHDL? I have been trying to learn Verilog.

Most FPGA/CPLD chip vendors have Sample SDRAM controllers - some have restrictions in that you may only use their IP on their specific chips -There are also a few free open cores out there - one in particualr that I started to work with is http://www.cmosexod.com/sdram.html. Latticealso seems to have some good cores which fit in a cpld ... I found not all cores are created equal when it comes to resources taken to get the job done.

I bet you Apple II guys could use that SDRAM with only 2 gals or a small CPLD. Just put the chip into self refresh mode between reads/writes. That wouldn't work for an Altair, since it can run without a clock.

I remember looking at this chip too. I think for me the best solution is using 16 of the $10 chips to get 16MB. My customers won't care and they will appreciate a board full of 32 pin DIPS more than some small finger nail sized thing.

Glenn: I would tend to agree with the MT48LC16M8A2 is the way to go. I also think Grant is right about only needing some small logic to address the IC. The SDRAM looks pretty basic too. There's some odd requirements to it's startup though which I'd have to think about, but I don't think it's a bad choice for what we want to use it for.

It's 3.3v, so we'd need some level translation obviously. I count 29 lines we will need to interface with. May be one or two that aren't need as I have just skimmed the data sheet at this point. So a GAL would work for addressing and refresh (the thing does CBR 'standard' rate it looks like) but not level translation unless there's some new ICs I don't know about. So a small CPLD would probably be our best choice, but I'd have to do a bit of research to tell for sure.

TSOP is good as I can solder that and we can also find DIP adapters pretty cheaply for prototyping.

I have Quartus but haven't really played around with it too much. I liked it because it had a schematic entry feature for design. No need to learn an HDL if you didn't want to. Altera also offers a pretty decent selection of parts. They also offer what they call 'Certified Design Centers' to help with different projects. I'll get on the phone with them and see if I can't find what part they would recommend and possibly talk with one of their Certified Design Centers and see what kind of price they would charge for creating the HDL program for us. If it's only a few hundred dollars then I say we let them do it and split the costs. That would save us a lot of time and in reality the program really shouldn't be that hard to create. Once we have a working model to work with we could modify the code as needed for other things. But at least we would have an example rather then starting from scratch and trying to learn everything at once.

Thoughts/ideas?

I'll post what I find here.

Grant: Why wouldn't this work for you? I don't follow.

PS - Grant: Can others see this Forum as well? I don't really care but if I send someone here I just want to know that they can see everything and follow along.

Right now only two people are allowed to see this section.

What I could do is make it invisible to EVERYONE, including you and Glenn. Then anyone who knows the URL would be able to see it. Would you like that?

In the end it would be more economical to use a CPLD. A more "proper" controller could be made AND some CPLDs will run on 3.3v yet still have 5v tollerant I/O (most chips don't allow inputs above +.3v VCC or so).

Since we're dealing with LS and HC TTL 3.3v logic will work just fine.

The Altair can run with the clock stopped. If you were to look at the memory chips, the read line is held low as long as the computer is stopped. If you "view" memory location 0xA5FB, then the address lines have 0xA5FB and the read line STAYS low. Same thing with any front panel setup.

There are some TTL dram controllers for the Altair, but a 3.3v CPLD with 5v logic kills two birds with one stone, and cheaply.

FYI - when talking to chip vendors

SDRAM is now considered old Skool by most chip vendors having come out in the later 90's - most of the IP is dated from around that time as well ... not saying it isn't useful but most chip vendors are now pushing DDR2 and DDR3 designs for which we have no use.

btw we need logic for two functions - one part is to control the SDRAM chip and the other part is what I call the personality module - the logic that talks too and possibily emualtes older style ram. This gets closer to how this module is being implemeted in a system and i see both parts of the required logic residing in the same CPLD.

Guys this is a blurb I put together to ask the opinion of this project from a few other folks awhile back

------------------------------------------------

I am considering making a cheap 8bit RAM card.

While my initial goal is to make a logical 16MB Slinky and or Ramworks III clone card I feel it could also be useful for other 8 bit platforms like AVR and PIC

My preferrred approach would be to use a small FPGA/CPLD (Xilinx XC3S100E or equiv ) mated with cheap SDRAM (non DDR).

The alternate approach is to use an ARM9 processor or AVR32 (vs FPGA) that already has a built-in SDRAM controller..

Do you see any major draw backs in either high level approach? I haven't really thought through the ARM9 approach very far but I think it should be doable. It would end up being more software driven vs hardware (verilog) but in the end probably more expensive to produce.



Here are some further details about the FPGA approach


I see this module in 3 logical parts in one FPGA

SDRAM Controller core
Std interface
Host interface


*SDRAM Controller IP*

There are a dozen or so SDRAM (non DDR) controllers out there from various chip vendors, 3rd party and open cores. One I found that I was going to base my project on was http://www.cmosexod.com/sdram.html - this seem to have good documentation for a noob like me and it's configurable for 32, 16. or 8 bit accesses. The downside is it also is configured for 32 bit wide memories (to give the flexibility of course). My first thought was to use this core and hardwire it to a chip like MT48LC16M8A2 to achieve two goals - 1) reduced logic required (to possibly fit in a CPLD vs FPGA) and 2) reduce the i/o required to get a small a pin package as possible or the other option is to just leave the core as is and use 32 bit wide memory.

I also just saw some controller IP on the lattice web site that looks like it is usable in small devices but I have not had time to review it yet.

**Standard interface (optional but I like the idea)* *

This would take the form of a sram "like" interface that would provide 24 bits address to the SDRAM controller module, provide what ever size data bus the SDRAM controller required. This interface is strictly internal only to the module. It would most likely be synchronous to the SDRAM controller and it would need to implement what ever control signals the SDRAM controller core required as well as take the input from the host interface IP. it also needs to handle the SDRAM clock and the host clock.

*Host interface*

Remaining available logic and i/o should be available to implement the host specific **personality** module. This could take the form of a simple sram like interface (preferably with zero wait state) or it could mimic an old dram (cas/ras interface). it would be up to the module to implement but it would talk to the standard interface the same way regardless of how it talked to the host. Since the connecting system typically will have a much slower clock then the sdram, zero wait state (from the host perspective) should be possible. The databus would only be 8 bits wide at this point.

The host logic needs to be 5v tolerant but everything else would/should be 3.3v


-------------------------------

Comments?

When you reading the note above you are probably wondering why I am mentiong FPGA vs CPLD etc ...

1) available logic
2) number of avaialble i/o's
3) $$$

some desgins I looked at from xilinx for example wouldn't even fit in the largest CPLD availalbe and even if they did they were way more expensive then the small fpga (logic slice)

anyway thats the designers job ...find the best device to fit the application ...

:o)

Use hardware for hardware solutions. The AVR32 is pretty big too.

Pretty big in what way?

AT32UC3A0512 - 32-bit Flash Microcontroller based on AVR32 UC core featuring 512K bytes Flash, 64 KBytes SRAM, 10/100 Ethernet MAC, full-speed (12 Mbps) USB 2.0 with On-The-Go (OTG) capability.

The AT32UC3A0512 also feature SRAM/SDRAM external bus interface.
The AT32UC3A devices deliver 80 Dhrystone MIPS (DMIPS) at 66 MHz and consume only 40 mA at 3.3V.

All in a LQFP144 - 20x20 mm package (same as that xilinx breakout board I already have) - 109 - 5v tolerant i/o pins

Actually the AVR32 would make the basis of a very nice co-processor card - the ram interface card could be the first option for it.


Well it's an option ;)

The main players are

Actel
Altera
Lattice
Xilinx


Henry, have a look at Lattice vs Altera or Xilinx - download the ispLever developement platform and have a look.

It is supposed to be easier to use vs Altera or Xilinx

Grant, who is your preferred chip vendor?

Glenn: I do have ISE and ispLever. I found ISE totally confusing. ispLever was a little better, but I still found it and Quartus a bit confusing. Probably due to the fact that I haven't really used anything close to them before. Grant found some videos that I've watched that helped a bit. Think they are still on my Site too if you'd like to see them.

After reading a few reviews and talking a few different people who do use those programs they have all pretty much told me that Quartus would be the best program for me since I don't want to learn an HDL. Quartus has a schematic entry interface like ispLever, but I had read that ispLever was going to get rid of theirs in the next version. So I'm pretty much stuck with Quartus I think.

I just spoke with a buddy of mine who is in school for electronics. I had been talking to him about this project as well off and on for the past few weeks. He said I may want to post the project on a freelance Site like GetAFreelancer.com in their electronics section. He said I should be able to find a programmer who would be willing to work on the project for just a few hundred since it's a really simple project.

Since we are all new to this it may be worth me posting the project ($10 and under) and finding a few guys to talk it over with and see what they think we would need and should do. Not that I don't think we could find a workable solution, but it may be a big time saver to talk it over with someone who has worked on different projects using PLDs, SDRAM and HDL software before.

Thoughts?

The problem with schematic entry in its purest form is that you have to make the entire design using logic chips. The Altera software has a schematic entry that allows you to design high level logic blocks in the HDL languages and draw schematic wires to and from the ports.

I'd like to learn one or the other, potentially VERY soon for the ramwall project. I'm split between Altera and Xilinx.

Its about 1x1. I have the dev board. I considered using it for a few things, but Atmel has lied to everyone for so long on when it would be available that I had to use an ARM.

It just seems like a hardware solution is what we need and getting that through a processor seems backwards. We would definitely need a CPLD in addition to the AVR32 any way. ;)

I am pretty sure Xilinx ISE lets you do the same thing - your top level file can be schematic, it will make symbols from the input/output ports of your HDL and you can connect the dots so to speak

Not sure if your familiar with Andre' Lamothe from the www.xgamestation.com web site. He has done a lot of this stuff before. I know he has looked at the various IDE's and his recommendation is typically Lattice esp for beginners ... thats what he has used for several CPLD based products on his web site - ymmv

FYI for Xilinx digilent has videos for ISE and so does Tony Burch http://www.burched.com/index.php

I had a real problem with Quartus and their licensesing files - finally got it straightened out - I wanted to see Alex Freeds latest FPGApple in it's native environment and it looks to me on first blush that ISE and Quartus appear vary similar in their toolset.

Henry, I don't have a problem if you want to test the waters on GetAFreelancer.com

So @ 60MHz you don't think the AVR32 would be fast enough to respond?

I havn't worked it out myself ...

I just got the http://www.atmel.com/dyn/products/to...p?tool_id=4114 board last week ... no time to goof around with it yet

btw ... I was was pretty surprised when I looked around a few months ago and didn't find anyone offering a board like we are proposing - I found one link on the Sparkfun forums where one of their guys at the time proposed the idea but nothing ever came of it from them. I could not even find a breakout board with just the premounted SDRAM - although I did find one vendor who has one in the wings it's not yet avallable for sale.

Mounting just the TSOP II SDRAM shouldn't be a big deal

An 8bit AVR at 20MHz is too slow for a 2MHz 8080.

The AVR is fast enough, but it would require a CPLD.

I interfaced a SCENIX directly to the ISA bus once. It required external address decoding. I think I was running at either 1 or 8MHz bus speed, but with like 30 wait states, so I'm not sure what the "final" speed was.

The INSTANT the ISA would access the scenix, the scenix would ask for wait states. It was tough. The scenix was running at 50MHz. Probably not as efficient though.

A CPLD and an AVR is MORE than fast enough. Its not that the AVR wasn't fast enough to process the data, but that its not fast enough to read the address, figure out what goes where, return data, etc. Too much to think about in the 1us allowed.

Thats the conclusion Alex Freed came to when he used a 20MHz avr for his Psuedo disk project although I thought that at 60Mhz it might just be fast enough ....

I think I am going to hook my test board up to the Apple II bus anyway - a good excercise to get to know my Logic Analyzer :)

What Logic Analyzer do you have? The DigiView?

I bought the 34 CHANNEL LA1034 LOGICPORT LOGIC ANALYZER

http://www.pctestinstruments.com/